1. Field of the Invention
The present invention relates to a correction circuit for generating a control signal for correcting a characteristic change caused by production conditions or physical conditions such as power supply and temperature in a transistor included in a semiconductor integrated circuit; and a delay circuit and a ring oscillator circuit including such a correction circuit. In particular, the present invention relates to a correction circuit, a delay circuit and a ring oscillator circuit which can be preferably used for, for example, generating a reference clock generation circuit (timing generation circuit) in, for example, an internal synchronization semiconductor memory device.
2. Description of the Related Art
Some delay circuits used as a timing generation circuit or the like in a CMOS semiconductor integrated circuit use a CMOS transistor. A delay circuit using a CMOS transistor uses signal transmission delay characteristics of the transistor which are determined by, for example, the driving load, the ON resistance, and the driving current of the transistor.
FIG. 6 shows a conventional delay circuit 100 using signal transmission delay characteristics of a transistor.
The delay circuit 100 includes a plurality of inverter circuits 103 connected to each other in series. In each inverter circuit 103, a p-channel (hereinafter, referred to as xe2x80x9cPchxe2x80x9d) transistor 101 and an n-channel (hereinafter, referred to as xe2x80x9cNchxe2x80x9d) transistor 102 are complementarily connected to each other as a pair between a supply terminal (supply voltage) and a ground terminal (ground voltage: earth). A gate of the Pch transistor 101 and a gate of the Nch transistor 102 included in each inverter circuit 103 each receive a signal from an input terminal or a signal from the previous-stage inverter circuit 103. A connection point between the Pch transistor 101 and the Nch transistor 102 outputs a signal to the subsequent-stage inverter circuit 103 or an output terminal.
When, for example, a signal from the input terminal or the previous-stage inverter circuit 103 is at an H level (supply voltage level), the Pch transistor 101 is turned OFF (non-conductive state) and the Nch transistor 102 is turned ON (conductive state). Therefore, the connection point between the Pch transistor 101 and the Nch transistor 102 outputs a signal at an L level (ground voltage level) to the subsequent-stage inverter circuit 103 or the output terminal. When a signal from the input terminal or the previous-stage inverter circuit 103 is at an L level, the Pch transistor 101 is turned ON and the Nch transistor 102 is turned OFF. Therefore, the connection point between the Pch transistor 101 and the Nch transistor 102 outputs a signal at an H level to the subsequent-stage inverter circuit 103 or the output terminal.
A delay time in the delay circuit 100 having the above-described structure will be described. A delay time is defined in a delay circuit as a time period from when an input signal voltage reaches the prescribed voltage until an output signal voltage reaches a prescribed voltage.
FIG. 7 is a timing diagram illustrating the timing of an input signal voltage and an output signal voltage in the delay circuit 100. In FIG. 7, the supply voltage is labeled as xe2x80x9cVCCxe2x80x9d, and the ground voltage is labeled as xe2x80x9cGNDxe2x80x9d. Here, the delay time is a time period in the delay circuit 100 from when the input signal voltage becomes xc2xd VCC until when the output signal voltage becomes xc2xd VCC.
The delay time in the delay circuit 100 greatly changes in accordance with the characteristics of the transistors (driving current, threshold level, etc.) included in the delay circuit. In general, the transistor characteristics are dispersed by, for example, supply voltage used for the delay circuit, ambient temperature of the delay circuit, and the production parameters of the delay circuit such as gate thickness, gate width, gate length and the like.
Thus, in the delay circuit 100 including the inverter circuit 103 shown in FIG. 6 having a simple structure, the delay time shown in FIG. 7 is dispersed by the supply voltage, ambient temperature, production parameters, and the like. A change in delay time caused by the dispersion does not necessarily have favorable results on the other circuits included in the semiconductor integrated circuit. For example, when a set delay time is set under certain conditions, the delay time may be too long or too short under other conditions.
Japanese Laid-Open Publication No. 7-38394 proposes a circuit for controlling the delay time.
FIG. 8 shows a conventional delay circuit 200 including a first correction circuit 210 and a second correction circuit 220 for controlling the delay time.
The delay circuit 200 includes a plurality of inverter circuits 205a and a plurality of inverter circuits 205b alternately connected in series. In the example of FIG. 8, a total of four inverter circuits (two inverter circuits 205a and two inverter circuits 205b) are provided. Each inverter circuit 205a includes a logic inversion circuit 203 which includes a Pch transistor 201 and an Nch transistor 202 complementarily connected as a pair, and a Pch transistor 204a connected in series between the logic inversion circuit 203 and the supply terminal. Each inverter circuit 205b includes a logic inversion circuit 203 which includes a Pch transistor 201 and an Nch transistor 202 complementarily connected as a pair, and an Nch transistor 204b connected in series between the logic inversion circuit 203 and the ground terminal.
A gate of the Pch transistor 201 and a gate of the Nch transistor 202 included in each logic inversion circuit 203 each receive a signal from an input terminal or a signal from the previous-stage logic inversion circuit 203. A connection point between the Pch transistor 201 and the Nch transistor 202 outputs a signal to the subsequent-stage logic inversion circuit 203 or an output terminal.
A gate electrode of the Pch transistor 204a included in the inverter circuit 205a receives a voltage (control signal) generated in the first correction circuit 210. A gate electrode of the Nch transistor 204b included in the inverter circuit 205b receives a voltage (control signal) generated in the second correction circuit 220.
In the delay circuit 200, the driving capability of each transistor or the like is adjusted such that the delay time is dominantly controlled by the Pch transistor 204a and the Nch transistor 204b. Thus, the delay time can be controlled in accordance with the characteristics of output voltages (control signals) of the first correction circuit 210 and the second correction circuit 220. As a result, the delay time caused by the delay circuit 200 can be substantially the same regardless of the conditions.
FIG. 9A is an equivalent circuit of an operation of the first correction circuit 210 shown in Japanese Laid-Open Publication No. 7-38394, and FIG. 9B is an equivalent circuit of an operation of the second correction circuit 220 also shown in Japanese Laid-Open Publication No. 7-38394.
The first correction circuit 210 includes a Pch transistor 301 and a resistor 302 connected in series in this order between the supply terminal and the ground terminal. A gate electrode of the Pch transistor 301 is connected to the ground voltage. A connection point (PO node) between the Pch transistor 301 and the resistor 302 outputs a voltage (control signal) PO. The second correction circuit 220 includes a resistor 304 and an Nch transistor 303 connected in series in this order between the supply terminal and the ground terminal. A connection point (NO node) between the resistor 304 and the Nch transistor 303 outputs a voltage (control signal) NO.
An operation of the first correction circuit 210 and the second correction circuit 220 having the above-described structure will be described. Output voltages of the first correction circuit 210 and the second correction circuit 220 are determined by the current-voltage characteristic of the transistor and the current-voltage characteristic of the resistor.
FIG. 10A is a graph illustrating the current-voltage characteristics of the elements themselves included in the first correction circuit 210 (transistor and resistor). FIG. 10B is a graph illustrating the current-voltage characteristics of the elements themselves included in the second correction circuit 220 (transistor and resistor).
In FIG. 10A, a characteristic 401 represents the current-voltage characteristic of the Pch transistor 301 included in the first correction circuit 210. The horizontal axis represents the PO output voltage at a certain gate voltage. When the PO output voltage is at the GND level, the voltage difference between the source electrode and the drain electrode is VCCxe2x88x92GND. When the PO output voltage is at the VCC level, the voltage difference between the source electrode and the drain electrode is 0. The vertical axis represents the current flowing between the source electrode and the drain electrode. A characteristic 402 represents the current-voltage characteristic of the resistor 302 included in the first correction circuit 210. The horizontal axis represents the PO output voltage. When the PO output voltage is at the GND level, the voltage difference at both ends of the resistor 302 is 0. When the PO output voltage is at the VCC level, the voltage difference between both ends of the resistor 302 is VCCxe2x88x92GND. The vertical axis represents the current flowing through the resistor 302.
In FIG. 10B, a characteristic 403 represents the current-voltage characteristic of the Nch transistor 303 included in the second correction circuit 220. The horizontal axis represents the NO voltage at a certain gate voltage. When the NO voltage is at the GND level, the voltage difference between the source electrode and the drain electrode is 0. When the NO voltage is at the VCC level, the voltage difference between the source electrode and the drain electrode is VCCxe2x88x92GND. The vertical axis represents the current flowing between the source electrode and the drain electrode. A characteristics 404 represents the current-voltage characteristic of the resistor 304 included in the second correction circuit 220. The horizontal axis represents the NO voltage. When the NO voltage is at the GND level, the voltage difference at both ends of the resistor 304 is VCCxe2x88x92GND. When the NO voltage is at the VCC level, the voltage difference between both ends of the resistor 304 is 0. The vertical axis represents the current flowing through the resistor 304.
In each of the first correction circuit 210 and the second correction circuit 220, the transistor and the resistor are connected in series. Therefore, the intersection a of the characteristic 401 and the characteristic 402 shown in FIG. 10A represents the output voltage and the output current from the first correction circuit 210. The intersection b of the characteristic 403 and the characteristic 404 shown in FIG. 10B represents the output voltage and the output current from the second correction circuit 220.
The principle of controlling the delay circuit time in the delay circuit 200 will be described. In the following description, an xe2x80x9cincreasexe2x80x9d (or a xe2x80x9cdecreasexe2x80x9d) of the capability of the transistor refers to an increase (or a decrease) of the current flowing between the source electrode and the drain electrode of the transistor.
The voltage output from the PO node (PO output voltage) in the first correction circuit 210 shown in FIG. 9A is sent as a control signal to the Pch transistor 204a shown in FIG. 8. The voltage output from the NO node (NO output voltage) in the second correction circuit 220 shown in FIG. 9B is sent as a control signal to the Nch transistor 204b shown in FIG. 8.
When, for example, the voltage of the PO node in FIG. 9A increases, the ON resistance of the Pch transistor 204a increases, since the output voltage therefrom (PO output voltage) is sent as a control signal to the gate electrode of the Pch transistor 204a shown in FIG. 8. As a result, the capability of the Pch transistor 204a decreases, and thus the delay time is extended. Conversely, when the voltage of the PO node in FIG. 9A decreases, the ON resistance of the Pch transistor 204a in FIG. 8 decreases. As a result, the capability of the Pch transistor 204a increases, and thus the delay time is shortened.
When, by contrast, the voltage of the NO node in FIG. 9B decreases, the ON resistance of the Nch transistor 204b increases, since the output voltage therefrom (NO output voltage) is sent as a control signal to the gate electrode of the Nch transistor 204b shown in FIG. 8. As a result, the capability of the Nch transistor 204b decreases, and thus the delay time is extended. Conversely, when the voltage of the NO node in FIG. 9B increases, the ON resistance of the Nch transistor 204b in FIG. 8 decreases. As a result, the capability of the Nch transistor 204b increases, and thus the delay time is shortened.
In the delay circuit 200 shown in FIG. 8, the delay time is extended when the capability of the Pch transistor 204a (FIG. 8) or the Nch transistor 204b decreases, and the delay time is shortened when the capability of the Pch transistor 204a or the Nch transistor 204b increases.
In consideration of the above, the relationship between the dispersion in ambient temperature and the delay time will be discussed. In general, when the ambient temperature of a circuit decreases, the threshold voltage of the transistor included in the circuit increases, but the capability of the transistor increases due to the semiconductor characteristics of the source electrode, the drain electrode, the channel region and the like. Accordingly, the delay time caused by the delay circuit 200 is shortened with the voltage of the NO node or the PO node being the same.
An operation of the delay circuit 200 will be discussed when the ambient temperature of the first correction circuit 210 and the second correction circuit 220 shown in FIGS. 9A and 9B decreases.
FIG. 11A is a graph illustrating a change in the current-voltage characteristics when the ambient temperature of the first correction circuit 210 decreases. As shown in FIG. 11A, when the ambient temperature of the first correction circuit 210 decreases, the capability of the Pch transistor 301 (FIG. 9A) increases. As a result, a current-voltage characteristic 401a of the transistor is changed into a current-voltage characteristic 401b, and thus the PO output voltage increases from voltage A to voltage B. In this manner, the voltage (control signal) from the PO node (FIG. 9A) increases.
FIG. 11B is a graph illustrating a change in the current-voltage characteristics when the ambient temperature of the second correction circuit 220 decreases. As shown in FIG. 11B, when the ambient temperature of the second correction circuit 220 decreases, the capability of the Nch transistor 303 (FIG. 9B) increases. As a result, a current-voltage characteristic 403a of the transistor is changed into a current-voltage characteristic 403b, and thus the NO output voltage decreases from voltage C to voltage D. In this manner, the voltage (control signal) from the NO node (FIG. 9B) decreases.
The PO output voltage (FIG. 9A) and the NO output voltage (FIG. 9B) are respectively input to the gate electrode of the Pch transistor 204a (FIG. 8) and the gate electrode of the Nch transistor 204b. Therefore, the ON resistance of each of the Pch transistor 204a and the Nch transistor 204b increases, and thus the capability of each of the Pch transistor 204a and the Nch transistor 204b decreases. As such, the decrease of the ambient temperature of the correction circuits acts on the delay circuit 200 so as to extend the delay time.
As described above, the decrease in the ambient temperature of the delay circuit 200 shortens the delay time with the voltage of the PO node and the voltage of the NO node (FIG. 8) being the same. However, the PO output voltage (FIG. 9A) and the NO output voltage (FIG. 9B) change so as to extend the delay time. Therefore, the action of shortening the delay time and the action of extending the delay time counteract each other, which allows the delay time to be kept the same.
FIG. 12A is a graph illustrating the relationship between the output voltage and the temperature (temperature-dependent characteristic of the output voltage) of the first correction circuit 210 (FIG. 9A). FIG. 12B is a graph illustrating the relationship between the output voltage and the temperature of the second correction circuit 220 (FIG. 9B). In the case where the first correction circuit 210 and the second correction circuit 220 provide the output voltage having the temperature-dependent characteristics shown in FIGS. 12A and 12B, the delay time can be controlled with respect to the varying temperature in the delay circuit 200 (FIG. 8).
The dispersion in production parameters occurring during the production of the semiconductor integrated circuit is handled in substantially the same manner. More specifically, when a characteristic is dispersed in the direction of decreasing the capability of the Pch transistor 204a and the Nch transistor 204b (FIG. 8), the output voltages (the PO output voltage and the NO output voltage) of the first correction circuit 210 and the second correction circuit 220 are changed in the direction of correcting the delay time in the delay circuit 200. When a characteristic is dispersed only in the Nch transistor 204b (FIG. 8), only the NO voltage which is input to the gate electrode of the Nch transistor 204b in the second correction circuit 220 (FIG. 9B) is changed. When a characteristic is dispersed only in the Pch transistor 204a (FIG. 8), only the PO voltage which is input to the gate electrode of the Pch transistor 204a in the first correction circuit 210 (FIG. 9A) is changed.
Next, an operation in the case where the supply voltage to the delay circuit 200 is changed will be discussed.
FIG. 13A is a graph illustrating a change in the current-voltage characteristic obtained when the supply voltage to the first correction circuit 210 is changed. As shown in FIG. 13A, when the supply voltage to the first correction circuit 210 is changed from voltage 1 to voltage 2, the voltage difference between the gate electrode and the source electrode of the Pch transistor 301 (FIG. 9A) included in the first correction circuit 210 is enlarged. As a result, the current-voltage characteristic 401a of the Pch transistor 301 is changed into a current-voltage characteristic 401c, and thus the PO output voltage is increased from voltage A to voltage B. In this manner, the voltage (control signal) from the PO node (FIG. 9A) increases.
FIG. 13B is a graph illustrating a change in the current-voltage characteristic obtained when the supply voltage to the second correction circuit 220 is changed. As shown in FIG. 13B, when the supply voltage to the second correction circuit 220 is changed from voltage 1 to voltage 2, the voltage difference between both ends of the resistor 304 included in the second correction circuit 220 (FIG. 9B) is enlarged. As a result, a current-voltage characteristic 404a of the resistor 304 is changed into a current-voltage characteristic 404b. The current-voltage characteristic 403a of the Nch transistor 303 is changed into a current-voltage characteristic 403c. As a result, the voltage (control signal) from the NO node shown in FIG. 9B is allowed to be not dependent on the supply voltage. For example, the NO output voltage is allowed to be constant at level C regardless of the supply voltage.
FIG. 14A is a graph illustrating the relationship between the output voltage and the supply voltage (supply voltage-dependent characteristic of the output voltage) of the first correction circuit 210 (FIG. 9A). FIG. 14B is a graph illustrating the relationship between the output voltage and the supply voltage of the second correction circuit 220 (FIG. 9B).
As described above, where the NO output voltage and the PO output voltage (FIG. 8) are constant, the delay time is shortened when the supply voltage to the delay circuit 200 increases. However, when the first correction circuit 210 and the second correction circuit 220 which provide output voltages having the supply voltage-dependent characteristics shown in FIGS. 14A and 14B are used, the PO output voltage and the NO output voltage act on the delay circuit 200 so as to extend the delay time. Therefore, the action of shortening the delay time and the action of extending the delay time counteract each other, which allows the delay time to be kept the same.
As described above, the conventional delay circuit 200 shown in FIG. 8 is provided with the first correction circuit 210 (FIG. 9A) and the second correction circuit 220 (FIG. 9B). Owing to such a structure, dispersion in delay time caused by the ambient temperature, supply voltage, production parameters of the semiconductor integrated circuit, and the like can be suppressed; or the dependency of the delay time on the ambient temperature, supply voltage, production parameters of the semiconductor integrated circuit, and the like can be freely controlled.
As described above, in the conventional delay circuit 200 including the first correction circuit 210 and the second correction circuit 220, dispersion in delay time can be suppressed, or the dependency of the delay time on the ambient temperature, supply voltage, production parameters, and the like can be freely controlled.
The resistance generated during the actual semiconductor process depends on temperature. For example, a diffusion resistance has a positive temperature dependency, and a polycrystalline silicon resistance has a negative temperature dependency. When the resistance has a positive temperature dependency, for example, when in FIG. 10, as the ambient temperature decreases, the resistance of the current-voltage characteristic decreases, the voltage from the PO node of the first correction circuit 210 (FIG. 9A) and the voltage from the NO node of the second correction circuit 220 (FIG. 9B) do not necessarily change in the direction for correcting the characteristic change of the transistor included in the delay circuit 200. As a result, the delay time is not allowed to be suppressed or controlled.
In the first correction circuit 210 (FIG. 9A) and the second correction circuit 220 (FIG. 9B), when the resistance is dispersed in accordance with the production parameters (for example, when, as shown in FIG. 15A, a current-voltage characteristic 402a of the resistor 302 is changed into a current-voltage characteristic 402b in the first correction circuit 210), the PO output voltage is changed from voltage A to voltage B as shown in FIG. 15A. When, as shown in FIG. 15B, the current-voltage characteristic 404a of the resistor 304 is changed into a current-voltage characteristic 404c in the second correction circuit 220, the NO output voltage is changed from voltage C to voltage D as shown in FIG. 15B.
When the PO output voltage B and the NO output voltage D do not exceed the threshold voltages of the Pch transistor 204a and the Nch transistor 204b (FIG. 8), respectively, the delay circuit 200 may not operate as a delay circuit. In the first correction circuit 210 and the second correction circuit 220 shown in FIGS. 9A and 9B, the PO output voltage and the NO output voltage undesirably may not exceed the respective threshold voltages of the Pch transistor 204a and the Nch transistor 204b shown in FIG. 8, depending on the manner that the resistance is dispersed.
When actually used, in the first correction circuit 210 and the correction circuit 220 (FIGS. 9A and 9B), a shoot-through current constantly flows between the supply terminal VCC and the ground terminal GND.
One proposal to avoid this is to set, in a semiconductor memory device or the like having a standby function, a signal for canceling the standby function (CEB signal), such that the device is in the standby-released state when the CEB signal is at the GND level (L level) and in the standby state when CEB signal is at the VCC level (H level).
FIG. 16 is a circuit diagram of a correction circuit system 230 for inputting a CEB signal to the first correction circuit 210 and the second correction circuit 220 (FIG. 8). The circuit configuration is disclosed in Japanese Laid-Open Publication No. 7-38394.
In the correction circuit system 230, a CEB signal is input to the gate electrode of the Pch transistor 301 included in the first correction circuit 210, and a signal inverted by an inverter circuit 305 is input to the gate electrode of the Nch transistor 303 included in the second correction circuit 220.
The correction circuit system 230 operates as follows, for example. When a CEB signal is changed from the H level to the L level so as to change the standby state into the standby-released state, the PO node shown in FIG. 16 is changed from the GND level to the PO output level (FIG. 10A). In the case where the voltage is changed in this manner, the current is changed as follows. When the voltage of the PO node (FIG. 16) is at the GND level, the current flowing between the source electrode and the drain electrode is as represented by level c (FIG. 10A). Until the PO output voltage shown in FIG. 10A is obtained, the current is changed from level c to level a (FIG. 10A) so as to charge the load connected to the PO node. The change of the current from level C to level a is based on the saturation region operation characteristics of the Pch transistor 301 shown in FIG. 16. Thus, level C and level a are substantially equal to each other.
Similarly, the NO node voltage shown in FIG. 16 is changed from the VCC level to the NO output voltage level (FIG. 10B). In the case where the voltage is changed in this manner, the current is changed as follows. The current flowing between the source electrode and the drain electrode is changed from level d to level b (FIG. 10B) so as to charge the load connected to the NO node. The change of the current from level d to level b is based on the saturation region operation characteristics of the Nch transistor 303 shown in FIG. 16. Thus, level d and level b are substantially equal to each other.
In the correction circuit system 230, a shoot-through current flows between the supply terminal VCC and the ground terminal GND while the CEB signal is at the GND level. This current is at level a and level b shown in FIGS. 10A and 10B. Generally in a semiconductor memory device and the like, the resistors and the capability of the transistors are adjusted to suppress such a shoot-through current, and thus to reduce the overall power consumption.
However, this involves the following problem. When, for example, the driving load of the PO node and the NO node shown in FIG. 16 is excessively large, if the above-mentioned shoot-through current is reduced, the time period in which the voltage changes from the GND level to the PO output voltage (FIG. 10A) and the time period in which the voltage changes from the VCC level to the NO output voltage (FIG. 10B) may be undesirably extended in the standby-released state in which the CEB signal is changed from the H level to the L level. This is caused because the current is restricted by the saturation region current of the Pch transistor 301 and the Nch transistor 303 (FIG. 16). The correction circuit system 230 provides the correction effect only when the PO output voltage (FIG. 10A) and the NO output voltage (FIG. 10B) are obtained. Therefore, when the time period until such a voltage is obtained from the standby-released state is too long, the correction circuit system 230 and the delay circuit including the correction circuit system 230 cannot be actually used for such a long time.
Conventionally, when the delay circuit needs to be used in a short time after the standby function is released, the current at level a (FIG. 10A) and the current at level b (FIG. 10B) are increased so that the saturation region current of the Pch transistor 301 and the Nch transistor 303 (FIG. 16) is increased. In this way, the current from level C to level a shown in FIG. 10A and the current from level d to level b shown in FIG. 10B are increased, which shortens the time period until the PO output voltage and the NO output voltage are obtained. However, this technique prevents reduction in the power consumption in the semiconductor memory device using the correction circuit system 230 (FIG. 16).
According to one aspect of the invention, a correction circuit, for generating a control signal for correcting a characteristic change of a first transistor, includes a control signal adjusting section including a constant voltage reduction element for determining either one of a maximum voltage and a minimum voltage of the control signal and a second transistor for determining a characteristic of the control signal, a gate electrode of the second transistor receiving a prescribed voltage; and a resistor section including two types of resistor elements having resistance values of different temperature dependency characteristics from each other, the resistor elements being connected in series. The constant voltage reduction element, the second transistor, and the resistor section are connected in series between a supply terminal and a ground terminal. The control signal is output from a connection point between the control signal adjusting section and the resistor section.
In one embodiment of the invention, the correction circuit further includes a further constant voltage reduction element for determining one of the maximum voltage and the minimum voltage of the control signal, wherein the second transistor and the further constant voltage reduction element are connected in parallel.
In one embodiment of the invention, the constant voltage reduction element and the further constant voltage reduction element include one of a transistor having a diode connection and a diode biased in a forward direction.
In one embodiment of the invention, the two types of resistor elements are a polycrystalline silicon resistor element and a diffusion resistor element formed of polycrystalline silicon containing impurities incorporated thereto.
In one embodiment of the invention, the correction circuit further includes a switching element for blocking a DC current path between the supply terminal and the ground terminal, wherein the constant voltage reduction element, the second transistor, the resistor section, and the switching element are connected in series.
In one embodiment of the invention, the constant voltage reduction element is a first p-channel transistor having a diode connection. The second transistor is a second p-channel transistor, and the prescribed voltage is a ground voltage. One of two ends of the resistor section is connected to the ground terminal. The control signal is output from a connection point between the control signal adjusting section and the other end of the resistor section.
In one embodiment of the invention, the constant voltage reduction element is a first p-channel transistor having a diode connection. The second transistor is a second p-channel transistor and the prescribed voltage is a ground voltage. The further constant voltage reduction element includes a plurality of third p-channel transistors connected in series, the plurality of p-channel transistors each having a diode connection. One of two ends of the resistor section is connected to the ground terminal. The control signal is output from a connection point between the other end of the resistor section and a parallel connection portion of the second transistor and the further constant voltage reduction element.
In one embodiment of the invention, the correction circuit further includes a third p-channel transistor for blocking a DC current path between the supply terminal and the ground terminal, wherein the constant voltage reduction element, the second transistor, the resistor section and the third p-channel transistor are connected in series.
In one embodiment of the invention, the correction circuit further includes a fourth p-channel transistor for blocking a DC current path between the supply terminal and the ground terminal, wherein the constant voltage reduction element, the second transistor, the resistor section and the fourth p-channel transistor are connected in series.
In one embodiment of the invention, the constant voltage reduction element is a first n-channel transistor having a diode connection. The second transistor is a second n-channel transistor, and the prescribed voltage is a supply voltage. One of two ends of the resistor section is connected to the supply terminal. The control signal is output from a connection point between the control signal adjusting section and the other end of the resistor section.
In one embodiment of the invention, the constant voltage reduction element is a first n-channel transistor having a diode connection. The second transistor is a second n-channel transistor and the prescribed voltage is a supply voltage. The further constant voltage reduction element includes a plurality of third n-channel transistors connected in series, the plurality of n-channel transistors each having a diode connection. One of two ends of the resistor section is connected to the supply terminal. The control signal is output from a connection point between the other end of the resistor section and a parallel connection portion of the second transistor and the further constant voltage reduction element.
In one embodiment of the invention, the correction circuit further includes a third n-channel transistor for blocking a DC current path between the supply terminal and the ground terminal, wherein the constant voltage reduction element, the second transistor, the resistor section and the third n-channel transistor are connected in series.
In one embodiment of the invention, the correction circuit further includes a fourth n-channel transistor for blocking a DC current path between the supply terminal and the ground terminal, wherein the constant voltage reduction element, the second transistor, the resistor section and the fourth n-channel transistor are connected in series.
According to another aspect of the invention, a delay circuit includes a logic inversion circuit; a correction circuit for generating a control signal for correcting a characteristic change of the logic inversion circuit; and a first transistor connected between the logic inversion circuit and a supply terminal. The correction circuit includes a control signal adjusting section including a constant voltage reduction element for determining either one of a maximum voltage and a minimum voltage of the control signal and a second transistor for determining a characteristic of the control signal, a gate electrode of the second transistor receiving a prescribed voltage; and a resistor section including two types of resistor elements having resistance values of different temperature dependency characteristics from each other, the resistor elements being connected in series. The constant voltage reduction element, the second transistor, and the resistor section are connected in series between a supply terminal and a ground terminal. The control signal is output from a connection point between the control signal adjusting section and the resistor section and input to a gate electrode of the first transistor.
According to still another aspect of the invention, a delay circuit includes a first logic inversion circuit; a second logic inversion circuit connected to the first logic inversion circuit in series; a first correction circuit for generating a first control signal for correcting a characteristic change in the first logic inversion circuit; a second correction circuit for generating a second control signal for correcting a characteristic change in the second logic inversion circuit; a p-channel transistor connected between the first logic inversion circuit and a supply terminal; and an n-channel transistor connected between the second logic inversion circuit and a ground terminal. The first correction circuit includes a first control signal adjusting section including a first constant voltage reduction element for determining a maximum voltage of the first control signal and a first transistor for determining a characteristic of the first control signal, a gate electrode of the first transistor receiving a first prescribed voltage; and a first resistor section including two types of resistor elements having resistance values of different temperature dependency characteristics from each other, the resistor elements being connected in series. The first constant voltage reduction element, the first transistor, and the first resistor section are connected in series between the supply terminal and the ground terminal. The first control signal is output from a connection point between the first control signal adjusting section and the first resistor section and input to a gate electrode of the p-channel transistor. The second correction circuit includes a second control signal adjusting section including a second constant voltage reduction element for determining a minimum voltage of the second control signal and a second transistor for determining a characteristic of the second control signal, a gate electrode of the second transistor receiving a second prescribed voltage; and a second resistor section including two types of resistor elements having resistance values of different temperature dependency characteristics from each other, the resistor elements being connected in series. The second constant voltage reduction element, the second transistor, and the second resistor section are connected in series between the supply terminal and the ground terminal. The second control signal is output from a connection point between the second control signal adjusting section and the second resistor section and input to a gate electrode of the n-channel transistor.
According to still another aspect of the invention, a ring oscillator circuit includes an odd number of logic inversion circuits connected in series; a first correction circuit for generating a first control signal for correcting a characteristic change in the odd number of logic inversion circuits; a second correction circuit for generating a second control signal for correcting a characteristic change in the odd number of logic inversion circuits; a plurality of p-channel transistors each connected between a corresponding one of the odd number of logic inversion circuits and a supply terminal; and a plurality of n-channel transistors each connected between a corresponding one of the odd number of logic inversion circuits and a ground terminal. Among the odd number of logic inversion circuits, a first logic inversion circuit and a second logic inversion circuit are connected in series in a feedback manner. The first correction circuit includes a first control signal adjusting section including a first constant voltage reduction element for determining a maximum voltage of the first control signal and a first transistor for determining a characteristic of the first control signal, a gate electrode of the first transistor receiving a first prescribed voltage; and a first resistor section including two types of resistor elements having resistance values of different temperature dependency characteristics from each other, the resistor elements being connected in series. The first constant voltage reduction element, the first transistor, and the first resistor section are connected in series between the supply terminal and the ground terminal. The first control signal is output from a connection point between the first control signal adjusting section and the first resistor section and input to a gate electrode of each of the p-channel transistors. The second correction circuit includes a second control signal adjusting section including a second constant voltage reduction element for determining a minimum voltage of the second control signal and a second transistor for determining a characteristic of the second control signal, a gate electrode of the second transistor receiving a second prescribed voltage; and a second resistor section including two types of resistor elements having resistance values of different temperature dependency characteristics from each other, the resistor elements being connected in series. The second constant voltage reduction element, the second transistor, and the second resistor section are connected in series between the supply terminal and the ground terminal. The second control signal is output from a connection point between the second control signal adjusting section and the second resistor section and input to a gate electrode of each of the plurality of n-channel transistors.
The present invention provides a correction circuit for generating a control signal for correcting a change in the transistor characteristics caused by production conditions and physical conditions including supply voltage and temperature. In such a correction circuit, two types of resistors having different temperature dependency characteristics of the resistance value (for example, a resistor having a positive temperature dependency and a resistor having a negative temperature dependency) are connected to each other in series, and thus a resistor section having a desired temperature dependency is produced. Thus, the dispersion in delay time caused by the temperature dependency of the resistors can be controlled.
According to the present invention, a transistor for receiving a prescribed gate voltage and a constant voltage reducing element including a transistor having a diode connection (or a diode biased in a forward direction) are connected in series. The transistor for receiving the prescribed gate voltage acts as an element for determining the characteristics of the output voltage of the correction circuit. The constant voltage reducing element is used to control the maximum possible voltage and the minimum possible voltage which are output from the correction circuit, so that the delay circuit is prevented from not operating due to the dispersion in production parameters of the resistors.
According to the present invention, a transistor for receiving a prescribed gate voltage and an additional constant voltage reducing element including a transistor having a diode connection (or a diode biased in a forward direction) are connected in parallel. While the output voltage from the correction circuit is changed to a desired voltage, the characteristics of the correction voltage can be determined by the additional constant voltage reducing element. Therefore, when the correction circuit has a standby function and is released from the standby state, the output voltage from the correction circuit can be changed to a desired voltage rapidly.
Accordingly, the present invention provides a stable delay time regardless of dispersion in supply voltage, temperature, production parameters or the like. Moreover, the dependency of the circuit on dispersion in supply voltage, temperature, production parameters or the like can be arbitrarily controlled to determine the delay time. In the case where a delay circuit is operated rapidly in a semiconductor integrated circuit having a standby function, the power consumption can be reduced. In the case where a boost circuit such as a charge pump or the like includes a ring oscillator circuit according to the present invention, the maximum operation current can be restricted.
Thus, the invention described herein makes possible the advantages of providing a correction circuit, a delay circuit and a ring oscillator circuit for controlling the dispersion in delay time caused by the temperature-dependent characteristic of the resistor, for preventing the delay circuit from not operating in accordance with the production parameters of the resistor, and, when the correction circuit has a standby function, for changing the output voltage from the correction circuit to a desired voltage in a standby-released state.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.